<tool command="asimut" envar="1">
	<row>
		<inputfile descr="input file" empty="0" color="#000000" hasgenfiles="1" hasdirfiles="1" hasprjfiles="1" editable="1" type="isinput"/>
		<patternfile descr="pattern file" empty="0" color="#000000" hasgenfiles="1" hasdirfiles="1" hasprjfiles="1" editable="1" type="ispattern"/>
		<outputfile descr="output file" empty="0" color="#000000" editable="1" addtogenfiles="1" type="isoutput"/>
	</row>
	<row>
		<note descr="* the input and output files must have extension" color="#FF0000"/>
	</row>	
	<options>
		<option opt="-b" descr="consider the root_file description as a behavioural description"/>
		<option opt="-backdelay" descr="use file delay_file.ext for delays backannotation,\nwhere ext is one of the extension specified in VH_DLYSFX" empty="0" editable="1"/>
		<option opt="-bdd" descr="use BDDs (Binary Decision Diagram) to represent expressions. Using this option\nmakes the simulation be two times faster but increases memory requirement"/>	
		<option opt="-c" descr="run only the compilation stage"/>
		<option opt="-core" descr="at the first error encountered, dump the state of the circuit in both an ascii file\n(suffixed .cor) and a binary save file (suffixed .sav) which can be used as initialization file\nin a further session. If the -nores option is specified a pattern file is also produced." empty="0" editable="1"/>
		<option opt="-dbg" descr="call the debugger (developper usage)" empty="1" editable="1"/>
		<option opt="-defaultdelay" descr="only null delays (no after clause in the VHDL file) are changed if\nbackannotated delays or fixed delays are specified"/>	
		<option opt="-fixeddelay" descr="all delays of the description are fixed to value" empty="0" editable="1"/>
		<option opt="-h" descr="display this help"/>
		<option opt="-i" descr="initialize all signals of the description with value. Or read a save file and use it to\ninitialize the state of the description before processing the first pattern" empty="0" editable="1"/>
		<option opt="-inspect" descr="produce a pattern file corresponding to the interface\nof the instance identified by instance-name" empty="0" editable="1"/>
		<option opt="-l" descr="print at most n characters for pattern labels. The default value for n is 15" empty="0" editable="1"/>
		<option opt="-nores" descr="do not generate result file"/>	
		<option opt="-p" descr="load at most n patterns from input pattern file each time. Using this feature reduces memory\nallocation when a great number of patterns are to be simulated. In addition after the n patterns have been\nprocessed, the simulation result is printed in the result pattern file. The default value for n is 0 which makes\nthe whole pattern file be loaded."/>	
		<option opt="-t" descr="trace signals when making BDDs (developper usage)"/>	
		<option opt="-transport" descr="use transport delay model (default is inertial)"/>	
		<option opt="-zerodelay" descr="all the delays of the VHDL description are supposed to be null delays"/>	
	</options>
	<command value="command options inputfile patternfile outputfile"/>
</tool>
